Compatibility Information
Designed For	Juniper M-series M10i M7i
Expansion / Connectivity
Compatible Slots	1 x expansion slot
Interfaces	10 x network - T1 - RJ-48
General
Designed For	M-series M10i M7i
Device Type	DSU/CSU
Enclosure Type	Plug-in module
Line Coding Format	AMI B8ZS
Line Rate	Fractional T-1/T-1
Max Transfer Rate	1.544 Mbps
Networking	HDLC Frame Relay PPP
Protocols & Specifications	HDLC
Miscellaneous
Compliant Standards	ETSI BSMI VCCI Class B ITE EN 60950 IEC 60950 EN55024 UL 60950 Third Edition CSA 22.2 No. 60950 EN55022 Class B IC CS-03 FCC Part 15 B EN 61000-4-4 EN 61000-4-2 EN 61000-4-3 EN 61000-4-6 FCC Part 68 EN 61000-4-5 EN 61000-4-11 RoHS
Modem
Connectivity Technology	Wired
Features	Bit error rate tester (BERT)
Framing Format	D4 ESF SF
Line Coding Format	AMI B8ZS
Line Rate	Fractional T-1/T-1
Max Transfer Rate	1.544 Mbps
Protocols & Specifications	HDLC
Networking
Compliant Standards	ANSI T1.403
Data Link Protocol	HDLC Frame Relay PPP

Juniper Networks 10 Port Channelized T1 to DS0 IQ PIC The Juniper Networks Channelized Physical Interface Cards (PICs) are designed to support the aggregation of large numbers of customer connections at the edge of the network for delivery into the service provider core

Juniper Networks 10 Port Channelized T1 to DS0 IQ PIC The Juniper Networks Channelized Physical Interface Cards (PICs) are designed to support the aggregation of large numbers of customer connections at the edge of the network for delivery into the service provider core. Service providers can maximize the utility of the existing infrastructure by channelizing from OC-12 down to DS0 speeds, enabling scarce and costly rack space to be optimized, maximizing profitability, revenue generation, and operational efficiency. The Channelized PICs leverage the strength of the industry-proven JUNOS operating system to ensure that every feature is available on every interface, regardless of bandwidth. The new generation of Juniper Networks Channelized PICs is based on the Q Performance Processor (QPP), a custom high-performance ASIC designed to deliver enhanced functionality. Known as Channelized Intelligent Queuing (IQ) PICs, their key features including multilevel channelization, comprehensive and granular QoS capabilities, and extensive instrumentation and diagnostics.